IC Layout Design & Verification - Classes Classified Ads in San Jose

IC Layout Design & Verification

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The most comprehensive IC Layout training programs in the industry, this program explores semiconductor process technologies from 0.18um BCD down to 23nm -14nm and covers Custom Analog, Digital, and Mixed-Signal layout skills. Class assignments and practice examples are realistic and are taken from actual design projects.

We welcome and accept: Corporate Tuition Reimbursement, Workers Compensation, California Training Benefit (CTB), Trade Adjustment Act (TAA), Workforce Investment Act (WIA), Vocational Rehab, and more...

For more information please contact Silicon Valley Polytechnic Institute; or call 408-436-3000.
August 29, 2016
1762 Technology Dr suite 228, San Jose, California
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IC Layout Design & Verification